Senior Validation Engineering Manager DDR

Senior Validation Engineering Manager DDR4/DD5

A leading chip and silicon IP provider is seeking an experienced Validation Manager to join its Memory Interface Chip business unit. In this role, you’ll collaborate with some of the industry’s top engineers and innovators to develop products that make data faster, more efficient, and more secure.

This is a hands-on technical management role and requires approximately 20–30% day-to-day technical work alongside leadership responsibilities.

Key Focus Areas & Technical Expertise

• Bench validation and electrical characterization of high-performance memory buffer chips
• DDR4/DDR5 memory characterization and validation
• Strong Python coding skills – must be capable of developing automation scripts and lab tools
• Experience with SerDes or PCIe/PCIe PHY high-speed interfaces
• Solid understanding of signal integrity, power integrity, and high-speed I/O characterization

Responsibilities

• Lead and directly contribute to hands-on bench validation and electrical characterization activities (20–30% of time)
• Manage and mentor a small team of 2–5 validation engineers, ensuring technical excellence and project alignment
• Partner with Design, Architecture, Verification, and Operations teams to deliver top-quality buffer chip products
• Develop and continuously refine validation methodologies, improving design coverage, efficiency, and time-to-market
• Collaborate with internal and external partners for test equipment sourcing, PCB fabrication, and assembly
• Develop automation frameworks and Python-based validation scripts for data collection and analysis
• Define and execute test methodologies to validate silicon designs against specifications
• Contribute to project planning, budgeting, and resource allocation

Qualifications

• B.S. or M.S. in Electrical Engineering or related field
• 5+ years of hands-on bench validation experience in semiconductor or system-level environments
• Proven experience with DDR4/DDR5 memory interfaces and processor/memory system architectures
• Demonstrated proficiency in Python scripting for validation, automation, and data analysis
• Background in SerDes or PCIe PHY characterization is highly desired
• Strong understanding of electrical characterization, signal integrity, and power integrity
• Experience managing small teams or leading technical projects as an individual contributor with leadership responsibilities
• Experience with ATE or system-level testing is a plus
• Excellent communication, organizational, and cross-functional collaboration skills

Location: Atlanta, GA or San Jose, CA (Relocation assistance available)

Duration: Fulltime

Salary Range: $136,000 to $252,600 (DOE)

Compensation: Medical, Vision and Dental Plan. Bonus: 20% RSUs: $145K total, vesting over 4 years.

Submit resume to ***email_hidden***

No 3rd party agencies or C2C

Abel Lara | 408.550.2800 x119

[email protected]